View UPD178018GC_8715999.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

m pd178004, 178006, 178016, 178018 mos integrated circuit the m pd178004, 178006, 178016 and 178018 are 8-bit single-chip cmos microcontrollers that incorporate hardware for digital tuning systems. the cpu uses the 78k/0 architecture and high-speed access to internal memory and control of peripheral hardware are easy to implement. also, the instructions used are the high-speed 78k/0 instructions, suitable for system control. the rich assortment of peripheral hardware includes an input/output port, 8-bit timer, a/d converter, serial interface, power-on clear circuits, as well as a pre-scaler for digital tuning, a pll frequency synthesizer and a frequency counter. the m pd178p018, one-time prom or eprom versions which can be operated in the same supply voltage range as for the mask rom versions, and various development tools, are also available. for more information on functions, refer to the following users manuals. be sure to read them when designing. m pd178018 subseries users manual: u11410e 78k/0 series users manual instruction: ieu-1372 features ? internal high-capacity rom and ram 8-bit single-chip microcontroller ? instruction cycle: 0.44 m s (4.5-mhz crystal oscillator used) ? large array of on-chip peripheral hardware general-purpose input/output port, a/d converter, serial interface, timer, frequency counter, power-on clear circuits. ? on-chip hardware for a pll frequency synthesizer. dual modulus pre-scaler, programmable divider, phase comparator, charge pump. ? vector interrupts: 17 ? supply voltage: v dd = 4.5 to 5.5 v (during pll operation) v dd = 3.5 to 5.5 v (during cpu operation, when the system clock is f x /2 or lower) v dd = 4.5 to 5.5 v (during cpu operation, when the system clock is f x ) items program memory data memory product name rom internal high-speed ram buffer ram internal expanded ram m pd178004 32 kbytes 1024 bytes 32 bytes not provided m pd178006 48 kbytes m pd178016 2048 bytes m pd178018 60 kbytes the information in this document is subject to change without notice. the mark shows major revised points. * document no. u11800ej2v1ds00 (2nd edition) date published march 1997 n printed in japan 1997 data sheet
m pd178004, 178006, 178016, 178018 2 applications car stereo, home stereo systems. ordering information part number package m pd178004gc- -3b9 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) m pd178006gc- -3b9 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) m pd178016gc- -3b9 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) m pd178018gc- -3b9 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) remark denotes the rom code number. also, the rom code number becomes e when the i 2 c bus is used. m pd178018 subseries expansion pd178018 subseries 80 pins prom : 60 kb ram : 3 kb pd178p018 80 pins rom : 60 kb ram : 3 kb pd178018 80 pins rom : 48 kb ram : 3 kb pd178016 80 pins rom : 48 kb ram : 1 kb pd178006 80 pins rom : 32 kb ram : 1 kb pd178004 m m m m m m
m pd178004, 178006, 178016, 178018 3 outline of function product name m pd178004 m pd178006 m pd178016 m pd178018 item internal rom (rom configuration) 32 kbytes 48 kbytes 60 kbytes memory (mask rom) (mask rom) (mask rom) internal high-speed ram 1024 bytes buffer ram 32 bytes internal expansion ram none 2048 bytes general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) instruction cycle with variable instruction execution time function 0.44 m s/0.88 m s/1.78 m s/3.56 m s/7.11 m s/14.22 m s (with 4.5-mhz crystal resonator) instruction set ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. i/o port total : 62 pins cmos input : 1 pin cmos i/o : 54 pins n-ch open-drain i/o : 4 pins n-ch open-drain output : 3 pins a/d converter 8-bit resolution 6 channels serial interface ? 3-wire/sbi/2-wire/i 2 c bus note mode selectable : 1 channel ? 3-wire serial i/o mode (with automatic transfer/receive function of up to 32 byte) : 1 channel timer ? basic timer (timer carry ff (10 hz)) : 1 channel ? 8-bit timer/event counter : 2 channels ? 8-bit timer (d/a converter: pwm output) : 1 channel ? watchdog timer : 1 channel buzzer (beep) output 1.5 khz, 3 khz, 6 khz vectored maskable interrupt internal: 8, external: 7 interrupt non-maskable interrupt internal: 1 software interrupt internal: 1 test input internal: 1 pll frequency division mode two types synthesizer ? direct division mode (vcol pin) ? pulse swallow mode (vcoh and vcol pins) reference frequency 12 types selectable by program (1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 25, 50 khz) charge pump error out output: 2 phase comparator unlock detectable by program frequency counter ? frequency measurement ? amifc pin: for 450-khz count ? fmifc pin: for 450-khz/10.7-mhz count d/a converter (pwm output) 8-/9-bit resolution 3 channels (shared by 8-bit timer) note when using the i 2 c bus mode (including when this mode is implemented by program without using the peripheral hardware), consult your local nec sales representative when you place an order for mask. (1/2)
m pd178004, 178006, 178016, 178018 4 product name m pd178004 m pd178006 m pd178016 m pd178018 item standby function ? halt mode ? stop mode reset ? reset by reset pin ? internal reset by watchdog timer ? reset by power-on clear circuit (3-value detection) ? detection of less than 4.5 v note (cpu clock: f x ) ? detection of less than 3.5 v note (cpu clock: f x /2 or less and on power application) ? detection of less than 2.5 v note (in stop mode) power supply voltage ? v dd = 4.5 to 5.5 v (with pll operating) ?v dd = 3.5 to 5.5 v (with cpu operating, cpu clock: f x /2 or less) ?v dd = 4.5 to 5.5 v (with cpu operating, cpu clock: f x ) package ? 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) note these voltage values are maximum values. the reset is actually executed at a voltage lower than these values. (2/2)
m pd178004, 178006, 178016, 178018 5 table of contents 1. pin configuration (top view) ................................................................................................ 6 2. block diagram ................................................................................................................ ........... 8 3. pin function list ............................................................................................................ ............ 9 3.1 port pins ................................................................................................................. ............... 9 3.2 pins other than port pins ............................................................................................ 10 3.3 input/output circuits and recommended connection of unused pins ..... 11 4. memory space ................................................................................................................. .......... 14 5. peripheral hardware function features ................................................................... 15 5.1 ports ..................................................................................................................... ................ 15 5.2 clock generator ........................................................................................................... .. 16 5.3 timer ..................................................................................................................... ................. 16 5.4 buzzer output control circuit ................................................................................. 18 5.5 a/d converter ............................................................................................................. ....... 19 5.6 serial interfaces ......................................................................................................... ... 19 5.7 pll frequency synthesizer ......................................................................................... 21 5.8 frequency counter ........................................................................................................ 2 2 6. interrupt functions and test functions ..................................................................... 23 6.1 interrupt functions ....................................................................................................... 23 6.2 test functions ............................................................................................................ ...... 26 7. standby function ............................................................................................................. ...... 27 8. reset function ............................................................................................................... .......... 27 9. instruction set .............................................................................................................. .......... 28 10. electrical specifications................................................................................................... 30 11. package drawings ............................................................................................................ ..... 46 12. recommended soldering conditions .............................................................................. 47 appendix a. development tools ............................................................................................. 48 appendix b. related documents ............................................................................................ 50
6 m pd178004, 178006, 178016, 178018 1. pin configuration (top view) ? 80-pin plastic qfp (14 14 mm, 0.65 mm pitch) m pd178004gc- -3b9, 178006gc- -3b9 m pd178016gc- -3b9, 178018gc- -3b9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0/sda0 p26/so0/sb1/sda1 p27/sck0/scl p132/pwm0 p133/pwm1 p134/pwm2 p40 p41 p42 p37 p36/beep p35 p34/ti2 p33/ti1 p32 p31 p30 p67 p66 p65 p64 p63 p62 p61 p60 p57 p56 p55 p54 reset v dd regosc x1 x2 gnd regcpu p06/intp6 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1 p00/intp0 p125 p124 p123 p122 p121 p120 gndport v dd port p43 p44 p45 p46 p47 amifc fmifc v dd pll vcoh vcol gndpll eo0 eo1 ic p50 p51 p52 p53 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 cautions 1. connect the internally connected (ic) pin to gnd directly. 2. connect v dd port and v dd pll pins to v dd . 3. connect the gndport and gndpll pins to gnd. 4. connect each of the regosc and regcpu pins to gnd via a 0.1- m f capacitor.
7 m pd178004, 178006, 178016, 178018 amifc : am intermediate frequency counter input an10-an15 : a/d converter input beep : buzzer output busy : busy output eo0, eo1 : error out output fmifc : fm intermediate frequency counter input gnd : ground gndpll : pll ground gndport : port ground ic : internally connected intp0-intp6 : interrupt inputs p00-p06 : port 0 p10-p15 : port 1 p20-p27 : port 2 p30-p37 : port 3 p40-p47 : port 4 p50-p57 : port 5 p60-p67 : port 6 p120-p125 : port 12 p132-p134 : port 13 pwm0-pwm2 : pwm output regcpu : regulator for cpu power supply regosc : regulator for oscillator circuit reset : reset input sb0, sb1 : serial data bus input/output sck0, sck1 : serial clock input/output scl : serial clock input/output sda0, sda1 : serial data input/output si0, si1 : serial data input so0, so1 : serial data output stb : strobe output ti1, ti2 : timer clock input vcol, vcoh : local oscillator input v dd : power supply v dd pll : pll power supply v dd port : port power supply x1, x2 : crystal oscillator connection
8 m pd178004, 178006, 178016, 178018 2. block diagram 8-bit timer/ event counter 1 8-bit timer/ event counter 2 8-bit timer 3 watchdog timer basic timer serial interface 0 serial interface 1 a/d converter interrupt control buzzer output system control ram 78k/0 cpu core rom 6 6 8 8 8 8 8 6 3 6 7 3 p00 p01-p06 d/a converter (pwm) pwm0/p132- pwm2/p134 frequency counter pll voltage regulator pll voltage regulator ti1/p33 ti2/p34 si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 reset x1 x2 v dd port gndport v dd reset cpu peripheral regosc regcpu gnd v osc v cpu ani0/p10- ani5/p15 intp0/p00- intp6/p06 beep/p36 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 12 port 13 p10-p15 p20-p27 p30-p37 p40-p47 p50-p57 p60-p67 p120-p125 p132-p134 amifc fmifc eo0 eo1 vcol vcoh v dd pll gndpll ic remark the internal rom and ram capacities depend on the version.
9 m pd178004, 178006, 178016, 178018 3. pin function list 3.1 port pins pin name i/o function after reset alternate function p00 input port 0. input only input intp0 p01-p06 i/o 7-bit input/output port. input/output mode can be specified bit-wise. input intp1-intp6 p10-p15 i/o port 1. input ani0-ani5 6-bit input/output port. input/output mode can be specified bit-wise. p20 i/o port 2. input si1 p21 8-bit input/output port. so1 p22 input/output mode can be specified bit-wise. sck1 p23 stb p24 busy p25 si0/sb0/sda0 p26 so0/sb1/sda1 p27 sck0/scl p30-p32 i/o port 3. input ? p33 8-bit input/output port. ti1 p34 input/output mode can be specified bit-wise. ti2 p35 ? p36 beep p37 ? p40-p47 i/o port 4. input ? 8-bit input/output port. input/output mode can be specified in 8-bit units. test input flag (krif) is set to 1 by falling edge detection. p50-p57 i/o port 5. input ? 8-bit input/output port. input/output mode can be specified bit-wise. p60-p63 i/o port 6. middle voltage n-ch open drain input ? 8-bit input/output port. input/output port. p64-p67 input/output mode can be leds can be driven directly. specified bit-wise. p120-p125 i/o port 12. input ? 6-bit input/output port. input/output mode can be specified bit-wise. p132-p134 output port 13. ? pwm0-pwm2 3-bit output port. n-ch open-drain output port.
10 m pd178004, 178006, 178016, 178018 3.2 pins other than port pins pin name i/o function after reset alternate function intp0-intp6 input external maskable interrupt inputs with specifiable valid edges (rising input p00-p06 edge, falling edge, both rising and falling edges). si0 input serial interface serial data input input p25/sb0/sda0 si1 p20 so0 output serial interface serial data output input p26/sb1/sda1 so1 p21 sb0 i/o serial interface serial data input/output input p25/si0/sda0 sb1 p26/so0/sda1 sda0 p25/si0/sb0 sda1 p26/so0/sb1 sck0 i/o serial interface serial clock input/output input p27/scl sck1 p22 scl p27/sck0 stb output serial interface automatic transmit/receive strobe output input p23 busy input serial interface automatic transmit/receive busy input input p24 ti1 input external count clock input to 8-bit timer (tm1) input p33 ti2 external count clock input to 8-bit timer (tm2) p34 beep output buzzer output input p36 ani0-ani5 input a/d converter analog input input p10-p15 pwm0-pwm2 output pwm output ? p132-p134 eo0, eo1 output error out output from charge pump of the pll frequency synthesizer ? ? vcol input inputs pll local band frequency (in hf, mf mode) ? ? vcoh input inputs pll local band frequency (in vhf mode) ? ? amifc input inputs am intermediate frequency counter ? ? fmifc input inputs fm intermediate frequency counter ? ? reset input system reset input ? ? x1 input system clock oscillation resonator connection ? ? x2 ? ?? regosc ? oscillation regulator. connected to gnd via a 0.1- m f capacitor. ? ? regcpu ? cpu power supply regulator. connected to gnd via a 0.1- m f capacitor. ? ? v dd ? positive power supply ? ? gnd ? ground ?? v dd port ? positive power supply for port block ? ? gndport ? ground for port block ? ? v dd pll ? positive power supply for pll ? ? gndpll ? ground for pll ? ? ic ? internally connected. connected to gnd or gndport. ? ?
11 m pd178004, 178006, 178016, 178018 3.3 input/output circuits and recommended connection of unused pins table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. refer to figure 3-1 for the configuration of the input/output circuit of each type. table 3-1. i/o circuit type of each circuit pin name i/o circuit type i/o recommended connections of unused pins p00/intp0 2 input connected to gnd or gndport p01/intp1-p06/intp6 8 i/o set in general-purpose input port mode by software and p10/ani0-p15/ani5 11-a individually connected to v dd , v dd port, gnd, or gndport p20/si1 8 via resistor. p21/so1 5 p22/sck1 8 p23/stb 5 p24/busy 8 p25/si0/sb0/sda0 10 p26/so0/sb1/sda1 p27/sck0/scl p30-p32 5 p33/ti1, p34/ti2 8 p35 5 p36/beep p37 p40-p47 5-g p50-p57 5 p60-p63 13 p64-p67 5 p120-p125 p132/pwm0-p134/pwm2 19 output set to low-level output by software and open eo0 dts-eo1 open eo1 dts-eo2 vcol, vcoh dts-amp input set to disabled status by software and open amifc, fmifc ic ? ? connected to gnd or gndport directly
12 m pd178004, 178006, 178016, 178018 figure 3-1. pin input/output circuit of list (1/2) in in/out input enable output disable data v dd p-ch n-ch type 2 type 5 schmitt-triggered input with hysteresis characteristics type 5-g type 11-a type 10 type 8 in/out output disable data v dd p-ch n-ch in/out output disable data v dd p-ch n-ch in/out open drain output disable data v dd p-ch n-ch in/out output disable data v dd p-ch n-ch p-ch comparator n-ch input enable v ref (threshold voltage) + _ remark all v dd and gnd in the above figures are the positive power supply and ground potential of the ports, and should be read as v dd port and gndport, respectively.
13 m pd178004, 178006, 178016, 178018 figure 3-1. pin input/output circuit of list (2/2) in type 19 type 13 type dts-eo2 type dts-amp type dts-eo1 data output disable in/out n-ch middle-voltage input buffer p-ch v dd pll v dd pll n-ch gndpll dw up out out n-ch dw up p-ch out v dd pll gndpll n-ch remark all v dd and gnd in the above figures are the positive power supply and ground potential of the ports, and should be read as v dd port and gndport, respectively.
14 m pd178004, 178006, 178016, 178018 4. memory space figure 4-1 shows the m pd178004, 178006, 178016 and 178018 memory map. figure 4-1. memory map notes 1. available only for m pd178016 and 178018 2 . the m pd178018 does not contain this use prohibited area. 3. the internal rom capacity depends on the version (see the table below). corresponding product internal rom last address name nnnnh m pd178004 7fffh m pd178006, 178016 bfffh m pd178018 efffh special function registers (sfr) 256 8 bits general-purpose registers 32 8 bits internal high-speed ram 1024 8 bits use prohibited buffer ram 32 8 bits use prohibited internal rom note 3 data memory space program memory space ffffh ff00h feffh fee0h fedfh fb00h faffh fae0h fadfh fac0h fabfh nnnnh + 1 nnnnh 0000h use prohibited internal expanded ram 2048 8 bits use prohibited note 2 fabfh f800h f7ffh f000h efffh nnnnh+1 program area callf entry area program area callt table area vectored table area nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h note 1
15 m pd178004, 178006, 178016, 178018 5. peripheral hardware function features 5.1 ports the following 3 types of i/o ports are available. ? cmos input (p00) : 1 ? cmos input/output (p01 to p06, port 1 to port 5, p64 to p67, port 12) : 54 ? n-channel open-drain input/output (p60 to p63) : 4 ? n-ch open drain output (port 13) : 3 total : 62 table 5-1. port functions input/output port pins. input/output specifiable bit-wise. dedicated input port pins port 0 p00 p01 to p06 input/output port pins. input/output specifiable bit-wise. port 1 p10 to p15 input/output port pins. input/output specifiable bit-wise. port 3 p30 to p37 input/output port pins. input/output specifiable bit-wise. port 2 p20 to p27 port 4 p40 to p47 input/output port pins. input/output specifiable in 8-bit units. test flag (krif) is set to 1 by falling edge detection. input/output port pins. input/output specifiable bit-wise. port 5 p50 to p57 n-channel open-drain input/output port pins. input/output specifiable bit-wise. led direct drive capability. port 6 p60 to p63 p64 to p67 port 12 p120 to p125 input/output port pins. input/output specifiable bit-wise. input/output port pins. input/output specifiable bit-wise. n-ch open drain output port. port 13 p132 to p134 pin name function name
16 m pd178004, 178006, 178016, 178018 5.2 clock generator the instruction execution time can be changed as follows. 0.44 m s/0.88 m s/1.78 m s/3.56 m s/7.11 m s/14.22 m s (@ 4.5-mhz crystal oscillator with system clock.) figure 5-1. clock generator block diagram x1 x2 f xx prescaler system clock oscillator clock to peripheral hardware other than the above. clock to the pll frequency synthesizer, basic timer and buzzer output control circuit. cpu clock (f cpu ) standby control circuit wait control circuit to intp0 sampling clock 2 f xx 2 2 f xx 2 3 f xx 2 4 f xx prescaler selector selector f x f x 2 stop scaler 5.3 timer the m pd178004, 178006, 178016 and 178018 incorporate 5 channels of the timer. ? basic timer : 1 channel ? 8-bit timer/event counter : 2 channel ? 8-bit timer (d/a converter) note : 1 channel ? watchdog timer : 1 channel note used is shared with the 8/9-bit resolution 3-channel d/a converter (pwm output). figure 5-2. basic timer block diagram divider 4.5 mhz inttmc
17 m pd178004, 178006, 178016, 178018 figure 5-3. 8-bit timer/event counter block diagram internal bus 8-bit compare register (cr10) 8-bit timer register 1 (tm1) clear match selector inttm1 inttm2 clear match selector selector selector selector 8-bit compare register (cr20) 8-bit timer register 2 (tm2) internal bus f xx /2-f xx /2 f x /2 9 11 ti1/p33 f xx /2-f xx /2 f x /2 9 11 ti2/p34 figure 5-4. 8-bit timer (d/a converter) block diagram 4.5 mhz clock generation block f pwm clear circuit comparator comparator comparator pwm data register 2 note (pwmr2) pwm data register 1 (pwmr1) pwm data register 0 (pwmr0) intpwm internal bus pwm duty setting block pwm mode select register p132/pwm0 p133/pwm1 p134/pwm2 b8 b0 pwm control register pwm bit pwm ck0 pwm md pwm st pwm res pwm 2se pwm 1se pwm 0se output select block output select block output select block 9-bit binary counter internal bus note the pwm data register 2 (pwmr2) is multiplexed with the pwm timer register (pwmtmr).
18 m pd178004, 178006, 178016, 178018 figure 5-5. watchdog timer block diagram control circuit 8-bit counter prescaler intwdt non-maskable interrupt request intwdt maskable interrupt request reset selector 2 f xx 4 2 f xx 5 2 f xx 6 2 f xx 7 2 f xx 8 2 f xx 9 2 f xx 11 2 f xx 3 5.4 buzzer output control circuit the clock with the following frequency can be output as a buzzer output. ? 1.5 khz/3 khz/6 khz (@ 4.5-mhz crystal oscillator with system clock) figure 5-6. buzzer output control circuit block diagram internal bus 1.5 khz 3 khz 6 khz tcl27 tcl26 tcl25 3 pm36 selector timer clock select register 2 port mode register 3 beep/p36 p36 output latch
19 m pd178004, 178006, 178016, 178018 5.5 a/d converter an a/d converter of 8-bit resolution 6 channels is incorporated. the following two types of the a/d conversion operation start-up methods are available. ? hardware start ? software start figure 5-7. a/d converter block diagram 5.6 serial interfaces 2 channels of the clocked serial interface are incorporated. ? serifal interface channel 0 ? serifal interface channel 1 table 5-2. types and functions of serial interface 3-wire serial i/o mode function serial interface channel 1 serial interface channel 0 (msb/lsb first switchable) (msb/lsb first switchable) (msb/lsb first switchable) 3-wire serial i/o mode with automatic transmission/ reception function sbi (serial bus interface) mode 2-wire serial i/o mode i 2 c bus mode (msb first) (msb first) (msb first) tap selector intad v dd intp3 internal bus gnd a/d conversion result register (adcr) control circuit succesive approximation register (sar) edge detection circuit ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 intp3/p03 selector sample & hold circuit voltage comparator resistor string
20 m pd178004, 178006, 178016, 178018 figure 5-8. serial interface channel 0 block diagram internal bus interrupt request signal generator handshake control circuit buffer ram serial clock control circuit selector serial counter serial i/o shift register 1 (sio1) automatic data transmit/ receive address pointer (adtp) automatic data transmit/receive interval specification register (adti) 5-bit counter intcsi1 f xx /2-f xx /2 8 si1/p20 so1/p21 stb/p23 busy/p24 sck1/p22 match figure 5-9. serial interface channel 1 block diagram busy/acknowledge output circuit output latch serial i/o shift register 0 (sio0) internal bus interrupt request signal generator serial clock counter bus release/command/ acknowledge detection circuit serial clock control circuit selector selector selector si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 intcsi0 f xx /2-f xx /2 8
21 m pd178004, 178006, 178016, 178018 5.7 pll frequency synthesizer figure 5-10. pll frequency synthesizer block diagram internal bus internal bus pll mode select register pwm data transfer register pll ns0 pll md0 pll md1 pll rf2 pll rf1 pll rf0 pll ul0 eoc on0 eo select register pll reference mode register pll unlock ff judge register pll rf3 2 input select block programmable divider phase comparator ( -det) unlock ff reference frequency generator 4.5 mhz 4 charge pump eo1 eo0 vcoh vcol mixer 2 f n f r pll data register (pllrl, pllrh, pllr0) f voltage control generator low pass filter note note note external circuit
22 m pd178004, 178006, 178016, 178018 5.8 frequency counter figure 5-11. frequency counter block diagram internal bus ifc md0 ifc ck1 ifc ck0 ifc jg0 if counter mode select register if counter gate judge register if counter control register ifc md1 ifc res ifc st input select block start/stop control block gate time control block if counter register (ifc) block 2 2 fmifc amifc
23 m pd178004, 178006, 178016, 178018 6. interrupt functions and test functions 6.1 interrupt functions there are 17 interrupt functions of three different kinds, as shown below. ? non-maskable interrupt : 1 ? maskable interrupt : 15 ? software interrupt : 1 table 6-1. interrupt source list non- maskable 0006h 0008h 000ah 000ch 000eh 0010h 0012h trigger internal/ external external internal 0004h 0014h internal vector table address interrupt source (b) basic configuration type note 2 (b) (a) (c) (d) maskable intp0 intp1 intp2 intp3 intp4 intp5 intp6 1 2 3 4 5 6 7 note 1 default priority name intcsi0 8 intwdt intwdt 0 interrupt type end of serial interface channel 0 transfer pin input edge detection watchdog timer overflow (interval timer mode selected) watchdog timer overflow (watchdog timer mode 1 selected) 0016h 9 intcsi1 end of serial interface channel 1 transfer 0018h 10 inttmc generation of match signal of basic timer 001ah 11 intpwm generation of match signal of 8-bit timer inttm1 generation of match signal of 8-bit timer/ event counter 1 12 001ch inttm2 generation of match signal of 8-bit timer/ event counter 2 001eh 13 14 intad end of conversion by a/d converter 0020h brk brk instruction execution 003eh software (e) internal notes 1. the default priority is a priority order when two or more maskable interrupts are generated simultaneously. 0 is the highest order and 14, the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1, respectively.
24 m pd178004, 178006, 178016, 178018 figure 6-1. interrupt function basic configuration(1/2) (a) internal non-maskable interrupt internal bus priority control circuit vector table address generator standby release signal interrupt request (c) external maskable interrupt (intp0) mk ie pr isp if priority control circuit vector table address generator sampling clock select register (scs) external interrupt mode register (intm0) edge detection circuit sampling clock internal bus standby release signal interrupt request (b) internal maskable interrupt mk internal bus ie pr isp if priority control circuit vector table address generator standby release signal interrupt request
25 m pd178004, 178006, 178016, 178018 figure 6-1. interrupt function basic configuration(2/2) (d) external maskable interrupt (except intp0) mk ie pr isp if priority control circuit vector table address generator external interrupt mode register (intm0, intm1) edge detection circuit internal bus standby release signal interrupt request (e) software interrupt priority control circuit vector table address generator internal bus interrupt request if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specification flag
26 m pd178004, 178006, 178016, 178018 6.2 test functions there is a test function as shown in table 6-2. table 6-2. test input source list figure 6-2. test function basic configuration if mk internal bus test input standby release signal if : test input flag mk : test mask flag test input source name trigger internal/external intpt4 port 4 falling edge detection external
27 m pd178004, 178006, 178016, 178018 7. standby function there are the following two standby functions to reduce the system power consumption. ? halt mode : the cpu operating clock is stopped. the average consumption current can be reduced by intermittent operation in combination with the normal operating mode. ? stop mode : the system clock oscillation is stopped. all operations by the system clock are stopped and current consumption can be considerably reduced. figure 7-1. stand-by function 8. reset function there are the following three reset methods. ? external reset input by reset pin ? internal reset by watchdog timer runaway time detection ? internal reset by power-on clear (poc). system clock operation stop mode (system clock oscillation stopped) halt mode (clock supply to cpu is stopped, oscillation continued) interrupt request interrupt request halt instruction stop instruction
28 m pd178004, 178006, 178016, 178018 9. instruction set (1) 8-bit instructions mov, xch, add addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note except r = a second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a r add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc mov mov add addc sub subc and or xor cmp inc dec b,c sfr mov mov dbnz mov add addc sub subc and or xor cmp saddr mov dbnz inc dec !addr16 mov psw mov mov push pop [de] ror4 rol4 [hl] mov [hl + byte] [hl + b] [hl + c] mov x c mulu divuw
29 m pd178004, 178006, 178016, 178018 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw note only when rp = bc, de or hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr (4) call instruction/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction compound instruction br call br callf callt br, bc, bnc bz, bnz bt, bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop second operand first operand ax rp sfrp saddrp !addr16 sp #word addw subw cmpw movw movw movw movw ax movw note movw movw movw movw movw xchw rp note sfrp movw saddrp movw !addr16 movw sp movw none incw decw push pop second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 mov1 mov1 mov1 mov1 bt bf btclr bt bf btclr set1 clr1 set1 clr1 bt bf btclr set1 clr1 bt bf btclr set1 clr1 bt bf btclr set1 clr1 set1 clr1 not1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1
30 m pd178004, 178006, 178016, 178018 10. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol test conditions rating unit power supply voltage v dd C0.3 to + 7.0 v input voltage v i1 excluding p60 to p63 C0.3 to v dd + 0.3 v v i2 p60 to p63 n-ch open-drain C0.3 to +16 v output voltage v o C0.3 to v dd + 0.3 v output withstand v bds p132 to p134 n-ch open-drain 16 v voltage analog input voltage v an p10 to p15 analog input pin C0.3 to v dd + 0.3 v output current high i oh 1 pin C10 ma p01 to p06, p30 to p37, p56, p57, p60 to p67, C15 ma p120 to p125 total p10 to p15, p20 to p27, p40 to p47, p50 to p55, C15 ma p132 to p134 total output current low i ol note 1 pin peak value 15 ma effective value 7.5 ma operating ambient t a C40 to +85 c temperature storage temperature t stg C65 to +150 c note effective value should be calculated as follows: [effective value] = [peak value] duty caution product quality may suffer if the absolute maximum rating is exceeded for even a single parameter even momentarily. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. parameter symbol test conditions min. typ. max. unit power supply voltage v dd1 during cpu operation and pll operation. 4.5 5.5 v v dd2 while the cpu is operating and the pll is stopped. 3.5 5.5 v cycle time: t cy 0.89 m s v dd3 while the cpu is operating and the pll is stopped. 4.5 5.5 v cycle time: t cy = 0.44 m s recommended supply voltage ranges (t a = C40 to +85 c) remark t cy : cycle time (minimum instruction execution time)
31 m pd178004, 178006, 178016, 178018 dc characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol test conditions min. typ. max. unit input voltage high v ih1 p10 to p15, p21, p23, 0.7 v dd v dd v p30 to p32, p35 to p37, p40 to p47, p50 to p57, p64 to p67, p120 to p125 v ih2 p00 to p06, p20, p22, 0.85 v dd v dd v p24 to p27, p33, p34, reset v ih3 p60 to p63 0.7 v dd 15 v (n-ch open-drain) input voltage low v il1 p10 to p15, p21, p23, 0 0.3 v dd v p30 to p32, p35 to p37, p40 to p47, p50 to p57, p64 to p67, p120 to p125 v il2 p00 to p06, p20, p22, 0 0.15 v dd v p24 to p27, p33, p34, reset v il3 p60 to p63 4.5 v v dd 5.5 v 0 0.3 v dd v (n-ch open-drain) 3.5 v v dd < 4.5 v 0 0.2 v dd v output voltage high v oh1 4.5 v v dd 5.5 v v dd C 1.0 v i oh = C1 ma 3.5 v v dd < 4.5 v v dd C 0.5 v i oh = C100 m a output voltage low v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 5.5 v, 0.4 2.0 v i oh = 15 ma p01 to p06, p10 to p15, v dd = 4.5 to 5.5 v, 0.4 v p20 to p27, p30 to p37, i ol = 1.6 ma p40 to p47, p64 to p67, p120 to p125, p132 to p134 v ol2 sb0, sb1, sck0 v dd = 4.5 to 5.5 v, 0.2 v dd v open-drain pulled-up (r = 1 k w ) remark the characteristics of an alternate function pin and a port pin are the same unless specified otherwise. (1/3) * *
32 m pd178004, 178006, 178016, 178018 dc characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) note when an input instruction is executed, the low-level input leakage current for p60 to p63 becomes C200 m a (max.) only in one clock cycle (at no wait). it remains at C3 m a (max.) for other than an input instruction. remark the characteristics of an alternate function pin and a port pin are the same unless specified otherwise. reference characteristics (t a = 25 c, v dd = 5 v) parameter symbol test conditions min. typ. max. unit input leakage i lih1 p00 to p06, p10 to p15, v in = v dd 3 m a current high p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p120 to p125, reset i lih2 p60 to p63 v in = 15 v 80 m a input leakage i lil1 p00 to p06, p10 to p15, v in = 0 v C3 m a current low p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p120 to p125, reset i lil2 p60 to p63 C3 note m a output leakage i loh p132 to p134 v out = 15 v 3 m a current high output leakage i lol p132 to p134 v out = 0 v C3 m a current low output off leak i lof eo0, eo1 v out = v dd , 1 m a current v out = 0 v par1ameter symbol test conditions min. typ. max. unit output current high i oh1 eo0 v out = v dd C1 v C4 ma eo1 (eocon0 = 1) C6 ma eo1 (eocon0 = 0) C2 ma output current low i ol1 eo0 v out = 1 v 6 ma eo1 (eocon0 = 1) 8 ma eo1 (eocon0 = 0) 3 ma (2/3) (1/2) *
33 m pd178004, 178006, 178016, 178018 dc characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol test conditions min. typ. max. unit power supply note 1 i dd1 while the cpu is operating t cy = 0.89 m s note 2 2.5 15 ma current and the pll is stopped i dd2 f x = 4.5 mhz operation t cy = 0.44 m s note 3 4.0 27 ma v dd = 4.5 to 5.5 v i dd3 while the cpu is operating t cy = 0.89 m s note 2 0.7 1.5 ma and the pll is stopped halt mode i dd4 pin x1 sine wave t cy = 0.44 m s note 3 1.0 2.0 ma input v in = v dd .v dd = 4.5 to 5.5 v f x = 4.5 mhz operation data hold v dr1 when the crystal is oscillating t cy = 0.44 m s 4.5 5.5 v power supply v dr2 t cy = 0.89 m s 3.5 5.5 v voltage v dr3 when the crystal oscillator is stopped 2.6 5.5 v when power off by power on clear is detected data hold i dr1 while the crystal oscillator t a = 25 c, v dd = 5v 2 4 m a power supply current i dr2 is stopped 230 m a notes 1. the port current is not included. 2. when the processor clock control register (pcc) is set at 00h, and the oscillation mode select register (osms) is set at 00h. 3. when pcc is set at 00h and osms is set at 01h. remarks 1. t cy : cycle time (minimum instruction execution time) 2. fx: system clock oscillator frequency. reference characteristics (t a = 25 c, v dd = 5 v) parameter symbol test conditions min. typ. max. unit power supply i dd5 during cpu operation t cy = 0.44 m s note 7ma current and pll operation. vcoh pin sine wave input f in = 130 mhz, v in = 0.15 v p-p note when the processor clock control register (pcc) is set at 00h, and the oscillation mode select register (osms) is set at 01h. remark t cy : cycle time (minimum instruction execution time) (3/3) (2/2) * * *
34 m pd178004, 178006, 178016, 178018 ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol test conditions min. typ. max. unit cycle time t cy f xx = f x /2 note 1 , f x = 4.5 mhz operation 0.89 14.22 m s (minimum instruction f xx = f x note 2 , 4.5 v dd 5.5 v 0.44 7.11 m s execution time) f x = 4.5 mhz operation 3.5 v dd < 4.5 v 0.89 7.11 m s ti1, ti2 input f ti 4.5 v dd 5.5 v 0 4.5 mhz frequency 3.5 v v dd 4.5 v 0 275 khz ti1, ti2 input high/ t tih , 4.5 v dd 5.5 v 111 ns low-level width t til 3.5 v v dd 4.5 v 1.8 m s interrupt input high/ t inth , intp0 8/f sam note 3 m s low-level width t intl intp1-intp6 10 m s reset low level t rsl 10 m s width notes 1. when oscillation mode selection (osms) register is set at 00h. 2. when osms is set at 01h. 3. in combination with bits 0 (scs0) and 1 (scs1) of sampling clock select register (scs), selection of f sam is possible between f xx /2 n , f xx /32, f xx /64 and f xx /128 (when n = 0 to 4). remarks 1. f xx : system clock frequency (f x or f x /2) 2. f x : system clock oscillation frequency t cy vs v dd (at f xx = f x /2 system clock operation) t cy vs v dd (at f xx = f x system clock operation) 60 10 2.0 1.0 0.5 0.4 0 1234 56 power supply voltage v dd [v] operation guaranteed range 60 10 2.0 1.0 0.5 0.4 0 1234 56 power supply voltage v dd [v] operation guaranteed range cycle time t cy [ m s] cycle time t cy [ m s]
35 m pd178004, 178006, 178016, 178018 (2) serial interface (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy1 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 1600 ns sck0 high-/low-level width t kh1 , 4.5 v v dd 5.5 v t kcy1 /2 C 50 ns t kl1 3.5 v v dd < 4.5 v t kcy1 /2 C 100 ns si0 setup time (to sck0 )t sik1 4.5 v v dd 5.5 v 100 ns 3.5 v v dd < 4.5 v 150 ns si0 hold time (from sck0 )t ksi1 400 ns so0 output delay time from sck0 ? t kso1 c = 100 pf note 300 ns note c is the load capacitance of so0 output line. (ii) 3-wire serial i/o mode (sck0 ... external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy2 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 1600 ns sck0 high-/low-level width t kh2 , 4.5 v v dd 5.5 v 400 ns t kl2 3.5 v v dd < 4.5 v 800 ns si0 setup time (to sck0 )t sik2 100 ns si0 hold time (from sck0 )t ksi2 400 ns so0 output delay time from sck0 ? t kso2 c = 100 pf note 300 ns sck0 at rising or falling edge time t r2 , t f2 1000 ns note c is the load capacitance of so0 output line.
36 m pd178004, 178006, 178016, 178018 (iii) sbi mode (sck0 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy3 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 3200 ns sck0 high-/low-level width t kh3 , 4.5 v v dd 5.5 v t kcy3 /2 C 50 ns t kl3 3.5 v v dd < 4.5 v t kcy3 /2 C 150 ns sb0, sb1 setup time (to sck0 )t sik3 4.5 v v dd 5.5 v 100 ns 3.5 v v dd < 4.5 v 300 ns sb0, sb1 hold time (from sck0 ) t ksi3 t kcy3 /2 ns sb0, sb1 output delay time from t kso3 r = 1 k w 4.5 v v dd 5.5 v 0 250 ns sck0 ? c = 100 pf note 3.5 v v dd < 4.5 v 0 1000 ns sb0, sb1 ? from sck0 t ksb t kcy3 ns sck0 ? from sb0, sb1 ? t sbk t kcy3 ns sb0, sb1 high-level width t sbh t kcy3 ns sb0, sb1 low-level width t sbl t kcy3 ns note r and c are the load resistance and load capacitance of sb0 and sb1 output line. (iv) sbi mode (sck0 ... external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy4 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 3200 ns sck0 high-/low-level width t kh4 , 4.5 v v dd 5.5 v 400 ns t kl4 3.5 v v dd < 4.5 v 1600 ns sb0, sb1 setup time (to sck0 )t sik4 4.5 v v dd 5.5 v 100 ns 3.5 v v dd < 4.5 v 300 ns sb0, sb1 hold time (from sck0 ) t ksi4 t kcy4 /2 ns sb0, sb1 output delay time from t kso4 r = 1 k w 4.5 v v dd 5.5 v 0 300 ns sck0 ? c = 100 pf note 3.5 v v dd < 4.5 v 0 1000 ns sb0, sb1 ? from sck0 t ksb t kcy4 ns sck0 ? from sb0, sb1 ? t sbk t kcy4 ns sb0, sb1 high-level width t sbh t kcy4 ns sb0, sb1 low-level width t sbl t kcy4 ns sck0 at rising or falling edge time t r4 , t f4 1000 ns note r and c are the load resistance and load capacitance of sb0 and sb1 output line.
37 m pd178004, 178006, 178016, 178018 (v) 2-wire serial i/o mode (sck0 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy5 r = 1 k w 1600 ns sck0 high-level width t kh5 c = 100 pf note t kcy5 /2 C 160 ns sck0 low-level width t kl5 4.5 v v dd 5.5 v t kcy5 /2 C 50 ns 3.5 v v dd < 4.5 v t kcy5 /2 C 100 ns sb0, sb1 setup time (to sck0 )t sik5 4.5 v v dd 5.5 v 300 ns 3.5 v v dd < 4.5 v 350 ns 400 ns sb0, sb1 hold time (from sck0 ) t ksi5 600 ns sb0, sb1 output delay time from t kso5 0 300 ns sck0 ? note r and c are the load resistance and load capacitance of sck0, sb0 and sb1 output line. (vi) 2-wire serial i/o mode (sck0 ... external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy6 1600 ns sck0 high-level width t kh6 650 ns sck0 low-level width t kl6 800 ns sb0, sb1 setup time (to sck0 )t sik6 100 ns sb0, sb1 hold time (from sck0 ) t ksi6 t kcy6 /2 ns sb0, sb1 output delay time from t kso6 r = 1 k w 4.5 v v dd 5.5 v 0 300 ns sck0 ? c = 100 pf note 3.5 v v dd < 4.5 v 0 500 ns sck0 at rising or falling edge time t r6 , t f6 1000 ns note r and c are the load resistance and load capacitance of sb0 and sb1 output line.
38 m pd178004, 178006, 178016, 178018 (vii) i 2 c bus mode (scl ... internal clock output) parameter symbol test conditions min. typ. max. unit scl cycle time t kcy7 r = 1 k w 10 m s scl high-level width t kh7 c = 100 pf note t kcy7 C 160 ns scl low-level width t kl7 t kcy7 C 50 ns sda0, sda1 setup time (to scl ) t sik7 200 ns sda0, sda1 hold time t ksi7 0ns (from scl ? ) sda0, sda1 output delay time t kso7 4.5 v v dd 5.5 v 0 300 ns (from scl ? ) 3.5 v v dd < 4.5 v 0 500 ns sda0, sda1 ? from scl or t ksb 200 ns sda0, sda1 from scl scl ? from sda0, sda1 ? t sbk 400 ns sda0, sda1 high-level width t sbh 500 ns note r and c are the load resistance and load capacitance of scl, sda0 and sda1 output line. (viii) i 2 c bus mode (scl ... external clock input) parameter symbol test conditions min. typ. max. unit scl cycle time t kcy8 1000 ns scl high-/low-level width t kh8, t kl8 400 ns sda0, sda1 setup time (to scl ) t sik8 200 ns sda0, sda1 hold time t ksi8 0ns (from scl ? ) sda0, sda1 output delay time t kso8 r = 1 k w 4.5 v v dd 5.5 v 0 300 ns from scl ? c = 100 pf note 3.5 v v dd < 4.5 v 0 500 ns sda0, sda1 ? from scl or t ksb 200 ns sda0, sda1 from scl scl ? from sda0, sda1 ? t sbk 400 ns sda0, sda1 high-level width t sbh 500 ns scl at rising or falling edge time t r8 , t f8 1000 ns note r and c are the load resistance and load capacitance of sda0 and sda1 output line.
39 m pd178004, 178006, 178016, 178018 (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy9 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 1600 ns sck1 high/low-level width t kh9 , 4.5 v v dd 5.5 v t kcy9 /2 C 50 ns t kl9 3.5 v v dd < 4.5 v t kcy9 /2 C 100 ns si1 setup time (to sck1 )t sik9 4.5 v v dd 5.5 v 100 ns 3.5 v v dd < 4.5 v 150 ns si1 hold time (from sck1 )t ksi9 400 ns so1 output delay time (from sck1 ?) t kso9 c = 100 pf note 300 ns parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy10 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 1600 ns sck1 high/low-level width t kh10 , 4.5 v v dd 5.5 v 400 ns t kl10 3.5 v v dd < 4.5 v 800 ns si1 setup time (to sck1 )t sik10 100 ns si1 hold time (from sck1 )t ksi10 400 ns so1 output delay time (from sck1 ? )t kso10 c = 100 pf note 300 ns sck1 at rising or falling edge time t r10 , t f10 1000 ns note c is the load capacitance of so1 output line. (ii) 3-wire serial i/o mode (sck1 ... external clock input) note c is the load capacitance of so1 output line.
40 m pd178004, 178006, 178016, 178018 (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy11 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 1600 ns sck1 high/low-level width t kh11 , 4.5 v v dd 5.5 v t kcy11 /2 C 50 ns t kl11 3.5 v v dd < 4.5 v t kcy11 /2 C 100 ns si1 setup time (to sck1 )t sik11 4.5 v v dd 5.5 v 100 ns 3.5 v v dd < 4.5 v 150 ns si1 hold time (from sck1 )t ksi11 400 ns so1 output delay time (from sck1 ? )t kso11 c = 100 pf note 300 ns stb from sck1 t sbd t kcy11 /2 C 100 t kcy11 /2 + 100 ns strobe signal high-level width t sbw t kcy11 / C 30 t kcy11 + 30 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 4.5 v v dd 5.5 v 100 ns (from busy signal detection timing) 3.5 v v dd < 4.5 v 150 ns sck1 ? from busy inactive t sps 2t kcy11 ns note c is the load capacitance of so1 output line. (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1 ... external clock input) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy12 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 1600 ns sck1 high/low-level width t kh12 , 4.5 v v dd 5.5 v 400 ns t kl12 3.5 v v dd < 4.5 v 800 ns si1 setup time (to sck1 )t sik12 100 ns si1 hold time (from sck1 )t ksi12 400 ns so1 output delay time (from sck1 ? )t kso12 c = 100 pf note 300 ns sck1 at rising or falling edge time t r12 , t f12 1000 ns note c is the load capacitance of so1 output line.
41 m pd178004, 178006, 178016, 178018 ac timing test point (excluding x1 input) ti timing interrupt input timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points t til t tih 1/f ti ti1, ti2 t intl t inth intp0-intp6 reset input timing t rsl reset
42 m pd178004, 178006, 178016, 178018 serial transfer timing 3-wire serial i/o mode: remark m = 1, 2, 9, 10 n = 2, 10 sbi mode (bus release signal transfer): t kcym t klm t khm sck0, sck1 si0, si1 so0, si1 t sikm t ksim t ksom input data output data t rn t fn t sik3,4 t kcy3,4 t kl3,4 t kh3,4 sck0 t sbl t sbh t ksb t sbk t ksi3, 4 t kso3,4 sb0, sb1 t r4 t f4
43 m pd178004, 178006, 178016, 178018 sbi mode (command signal transfer): 2-wire serial i/o mode: i 2 c bus mode: t sik3,4 t kcy3,4 t kl3,4 t kh3,4 sck0 t ksb t sbk t ksi3,4 t kso3,4 sb0, sb1 t r4 t f4 t kso5,6 t sik5,6 t kcy5,6 t kl5,6 t kh5,6 sck0 t ksi5,6 sb0, sb1 t f6 t r6 scl sda0, sda1 t sbh t kl7, 8 t sbk t f8 t r8 t kcy7, 8 t ksi7, 8 t kh7, 8 t sik7, 8 t kso7, 8 t sbk t ksb t ksb
44 m pd178004, 178006, 178016, 178018 3-wire serial i/o mode with automatic transmit/receive function: t sbw t sbd t kcy11 , 12 t kh11 , 12 t ksi11 , 12 t kso11 , 12 t sik11 , 12 d2 d1 d0 d7 d7 d2 d1 d0 so1 si1 sck1 stb t r12 t kl11 , 12 t f12 3-wire serial i/o mode with automatic transmit/receive function (busy processing): t bys sck1 t sps busy (active high) 789 note 10 note 10+n note 1 t byh note the signal is not actually driven low here; it is shown as such to indicate the timing.
45 m pd178004, 178006, 178016, 178018 a/d converter charateristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol test conditions min. typ. max. unit resolution 8 8 8 bit conversion total 3.0 lsb error conversion time t conv 22.2 44.4 m s sampling time t samp 15/f xx m s analog input v ian 0v dd v voltage remarks 1. f xx : system clock frequency (f x /2) 2. f x : system clock oscillation frequency pll characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol test conditions min. typ. max. unit operating f in1 vcol pin mf mode sine wave input v in = 0.1 v p-p 0.5 3 mhz frequency f in2 vcol pin hf mode sine wave input v in = 0.2 v p-p 9 55 mhz f in3 vcoh pin vhf mode sine wave input v in = 0.15 v p-p 60 160 mhz ifc characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol test conditions min. typ. max. unit operating f in4 amifc pin amif count mode 0.4 0.5 mhz frequency sine wave input v in = 0.1 v p-p note f in5 fmifc pin fmif count mode 10 11 mhz sine wave input v in = 0.1 v p-p note f in6 fmifc pin amif count mode 0.4 0.5 mhz sine wave input v in = 0.1 v p-p note note the condition of a sine wave input of v in = 0.1 v p-p is the standard value for operation of this device during stand-alone operation, so in consideration of the effect of noise, it is recommended that operation be at an input amplitude condition of v in = 0.15 v p-p . * * *
46 m pd178004, 178006, 178016, 178018 11. package drawings a m f b 60 61 40 k l 80 pin plastic qfp (14 14) 80 1 21 20 41 g d c detail of lead end s q p m i h j 55 n s80gc-65-3b9-3 item millimeters inches a b c d f g h i j k l 17.2 0.4 14.0 0.2 0.8 0.30 0.10 0.13 14.0 0.2 0.677 0.016 0.031 0.031 0.005 0.026 (t.p.) 0.551 note m n 0.10 0.15 1.6 0.2 0.65 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 0.063 0.008 0.012 0.551 0.8 0.2 0.031 p 2.7 0.106 0.677 0.016 17.2 0.4 0.8 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008
47 m pd178004, 178006, 178016, 178018 12. recommended soldering conditions this product should be soldered and mounted under the conditions recommended in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact an nec sales representa- tive. table 12-1. surface mounting type soldering conditions m pd178004gc- -3b9 : 80-pin plastic qfp (14 14 mm, 0.65 mm pitch) m pd178006gc- -3b9 : 80-pin plastic qfp (14 14 mm, 0.65 mm pitch) m pd178016gc- -3b9 : 80-pin plastic qfp (14 14 mm, 0.65 mm pitch) m pd178018gc- -3b9 : 80-pin plastic qfp (14 14 mm, 0.65 mm pitch) package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), number of times: three times max. package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above), number of times: three times max. solder bath temperature : 260 c max., duration : 10 sec. max., number of times : once, preheating temperature : 120 c max. (package surface temperature) pin temperature: 300 c max. duration: 3 sec. max. (per pin row) infrared reflow vps wave soldering partial heating ir35-00-3 vp15-00-3 ws60-00-1 recommended condition symbol soldering conditions soldering method caution do not use different soldering method together (except for partial heating).
48 m pd178004, 178006, 178016, 178018 appendix a. development tools the following development tools are available for system development using the m pd178018 subseries. language processing software ra78k/0 notes 1, 2, 3, 4 78k/0 series common assembler package cc78k/0 notes 1, 2, 3, 4 78k/0 series common c compiler package df178018 notes 1, 2, 3, 4 m pd178018 subseries common device file cc78k/0-l notes 1, 2, 3, 4 78k/0 series common c compiler library source file prom writing tools pg-1500 prom programmer pg-178p018gc pa-178p018kk-t pg-1500 controller notes 1, 2 pg-1500 control program debugging tools ie-78000-r in-circuit emulator common to 78k/0 series ie-78000-r-a in-circuit emulator common to 78k/0 series (for the integration debugger) ie-78000-r-bk break board common to 78k/0 series ie-178018-r-em emulation board common to m pd178018 subseries ep-78230gc-r emulation probe common to m pd78234 subseries ev-9200gc-80 socket for mounting on target system board created for 80-pin plastic qfp (gc-3b9 type) ev-9900 jig used when removing the m pd178p018kk-t from the ev-9200gc-80. sm78k0 notes 5, 6, 7 78k/0 series common system simulator id78k0 notes 4, 5, 6, 7 integration debugger for ie-78000-r-a sd78k/0 notes 1, 2 ie-78000-r screen debugger df178018 notes 1, 2, 4, 5, 6, 7 m pd178018 subseries device file real-time os rx78k/0 notes 1, 2, 3, 4 78k/0 series real-time os mx78k0 notes 1, 2, 3, 4 78k/0 series os programmer adapters connected to a pg-1500 notes 1. pc-9800 series (ms-dos tm ) based 2. ibm pc/at tm and compatible (pc dos tm /ibm-dos tm /ms-dos) based 3. hp9000 series 300 tm based 4. hp9000 series 700 tm (hp-ux tm ) based, sparcstation tm (sunos tm ) based, ews-4800 series (ews-ux/v) based 5. pc-9800 series (ms-dos + windows tm ) based 6. ibm pc/at and compatible (pc dos/ibm dos/ms-dos + windows) based 7. news tm (news-os tm ) based *
49 m pd178004, 178006, 178016, 178018 fuzzy inference development support system fe9000 note 1 /fe9200 note 2 fuzzy knowledge data creation tool ft9080 note 1 /ft9085 note 3 translator fi78k0 notes 1, 3 fuzzy inference module fd78k0 notes 1, 3 fuzzy inference debugger notes 1. pc-9800 series (ms-dos) based 2. ibm pc/at and its compatibles (pc dos/ibm dos/ms-dos + windows) based 3. ibm pc/at and its compatibles (pc dos/ibm dos/ms-dos) based remarks 1. please refer to the 78k/0 series selection guide (u11126e) for information on third party development tools. 2. the ra78k/0, cc78k/0, sd78k/0, id78k/0, sm78k/0 and rx78k/0 are used in combination with the df178018.
50 m pd178004, 178006, 178016, 178018 appendix b. related documents device documents title document no. document no. (japanese) (english) m pd178018 subseries users manual u11410j u11410e 78k/0 series users manualinstruction ieu-849 ieu-1372 78k/0 series instruction set u10904j 78k/0 series instruction table u10903j m pd178018 subseries special function register table to be prepared 78k/0 series application note basics (ii) u10121j u10121e development tool documents (users manual) title document no. document no. (japanese) (english) ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k/0 c compiler operation u11517j u11517e language u11518j u11518e cc78k/0 c compiler application notes programming know-how eea-618 eea-1208 cc78k series library source file eeu-777 pg-1500 prom programmer eeu-651 eeu-1335 pg-1500 controller pc-9800 series (ms-dos) based eeu-704 eeu-1291 pg-1500 controller ibm pc series (pc dos) based eeu-5008 u10540e ie-78000-r eeu-810 u11376e ie-78000-r-a u10057j u10057e ie-78000-r-bk eeu-867 eeu-1427 ie-178018-r-em u10668j u10668e ep-78230 eeu-985 eeu-1515 sm78k0 system simulator windows based reference u10181j u10181e sm78k series system simulator u10092j u10092e id78k0 integrated debugger ews based reference u11151j u11151e id78k0 integrated debugger pc based reference u11539j u11539e id78k0 integrated debugger windows based guide u11649j u11649e sd78k/0 screen debugger pc-9800 series (ms-dos) based introduction eeu-852 reference u10952j sd78k/0 screen debugger ibm pc/at (pc dos) based introduction eeu-5024 eeu-1414 reference u11279j eeu-1413 external parts user open interface specifications caution the contents of the above documents are subject to change without notice. please ensure that the latest versions are used in design work, etc. *
51 m pd178004, 178006, 178016, 178018 related documents for embedded software (users manual) title document no. document no. (japanese) (english) 78k/0 series realtime os basics u11537j installation u11536j technical u11538j 78k/0 series os mx78k0 basics eeu-5010 fuzzy knowledge data creation tool eeu-829 eeu-1438 78k/0, 78k/ii, 87ad series eeu-862 eeu-1444 fuzzy inference development support systemtranslator 78k/0 series fuzzy inference development support system fuzzy inference module eeu-858 eeu-1441 78k/0 series fuzzy inference development support system eeu-921 eeu-1458 fuzzy inference debugger other documents title document no. document no. (japanese) (english) ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality guides on nec semiconductor devices c11531j c11531e nec semiconductor device reliability and quality control c10983j c10983e electrostatic discharge (esd) test mem-539 semiconductor device quality assurance guide c11893j mei-1202 microcomputer-related product guide (products by other manufacturers) u11416j caution the contents of the above documents are subject to change without notice. ensure that the latest versions are used in design work, etc.
52 m pd178004, 178006, 178016, 178018 [memo]
53 m pd178004, 178006, 178016, 178018 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
54 m pd178004, 178006, 178016, 178018 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
55 m pd178004, 178006, 178016, 178018 [memo]
56 m pd178004, 178006, 178016, 178018 purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. m4 96.5 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re- export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation.

▲Up To Search▲

Price & Availability of UPD178018GC

	To Download UPD178018GC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .